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XMEGA A [MANUAL]
8077I–AVR–11/2012
13.10 Clock and Event Output
It is possible to output the peripheral clock and event channel 0 events to a pin. This can be used to clock, control, and
synchronize external functions and hardware to internal device timing. The output port pin is selectable. If an event
occurs, it remains visible on the port pin as long as the event lasts; normally one peripheral clock cycle.
13.11 Multi-pin Configuration
The multi-pin configuration function is used to configure multiple port pins using a single write operation to only one of the
port pin configuration registers. A mask register decides which port pin is configured when one port pin register is written,
while avoiding several pins being written the same way during identical write operations.
13.12 Virtual Ports
Virtual port registers allow the port registers to be mapped virtually in the bit-accessible I/O memory space. When this is
done, writing to the virtual port register will be the same as writing to the real port register. This enables the use of I/O
memory-specific instructions, such as bit-manipulation instructions, on a port register that normally resides in the
extended I/O memory space. There are four virtual ports, and so four ports can be mapped at the same time.
13.13 Register Descriptions – Ports
13.13.1 DIR – Data Direction register
Bit 7:0 – DIR[7:0]: Data Direction
This register sets the data direction for the individual pins of the port. If DIRn is written to one, pin n is configured as an
output pin. If DIRn is written to zero, pin n is configured as an input pin.
13.13.2 DIRSET – Data Direction Set register
Bit 7:0 – DIRSET[7:0]: Port Data Direction Set
This register can be used instead of a read-modify-write to set individual pins as output. Writing a one to a bit will set the
corresponding bit in the DIR register. Reading this register will return the value of the DIR register.
13.13.3 DIRCLR – Data Direction Clear register
Bit 7:0 – DIRCLR[7:0]: Port Data Direction Clear
Bit
7
6
5
4
3
2
1
0
+0x00
DIR[7:0]
Read/Write
R/W
Initial Value
0
Bit
7
6
5
432
10
+0x01
DIRSET[7:0]
Read/Write
R/W
Initial Value
0
Bit
7
6
5
4
3
2
1
0
+0x02
DIRCLR[7:0]
Read/Write
R/W
Initial Value
0
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